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july 2009 doc id 16067 rev 1 1/57 1 STA2500D bluetooth? v2.1 + edr ("lisbon ") for automotive applications features based on ericsson technology licensing baseband core (ebc) bluetooth? specification compliance: v2.1 + edr (?lisbon?) ? point-to-point, point-to-multipoint (up to 7 slaves) and scatternet capability ? support acl and sco links ? extended sco (esco) links ? faster connection hw support for packet types ? acl: dm1, dm3, dm5, dh1, dh3, dh5, 2- dh1, 2-dh3, 2-dh5, 3-dh1, 3-dh3, 3-dh5 ? sco: hv1, hv3 and dv ? esco: ev3, ev4, ev5, 2-ev3, 2-ev5, 3- ev3, 3-ev5 adaptive frequency hopping (afh) channel quality driven data rate (cqddr) ?lisbon? features ? encryption pause/resume (epr) ? extended inquiry response (eir) ? link supervision time out (lsto) ? secure simple pairing ? sniff subrating ? quality of service (qos) packet boundary flag erroneous data delivery transmit power ? power class 2 and power class 1.5 (above 4 dbm) ? programmable output power ? power class 1 compatible hci ? hci h4 and enhanced h4 transport layer ? hci proprietary commands (e.g. peripherals control) ? single hci command for patch/upgrade download ? esco over hci supported supports pitch-period error concealment (ppec) efficient and flexible support for wlan coexistence scenarios low power consumption ? ultra low power architecture with 3 different low-power levels ? deep sleep modes, including host-power saving feature ? dual wake-up mechanism: initiated by the host or by the bluetooth device communication interfaces ? fast uart up to 4 mhz ? flexible spi interface up to 13 mhz ? pcm interface ? up to 10 additional flexibly programmable gpios ? external interrupts possible through the gpios ?fast i 2 c interface as master clock support ? system clock input (digital or sine wave) at 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4 mhz ? low power clock input at 3.2 khz, 32 khz and 32.768 khz arm7tdmi cpu memory organization ? on chip ram, including provision for patches ? on chip rom, preloaded with sw up to hci ciphering support up to 128-bit key single power supply with internal regulators for core voltage generation supports 1.65 v to 2.85 v i/o systems auto calibration (vco, filters) table 1. device summary order code package packing STA2500D STA2500Dtr lfbga48 tr ay tape and reel lfbga48 (6x6x1.4mm; 0.8mm pitch) www.st.com
contents STA2500D 2/57 doc id 16067 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 block diagram and electrical sc hematic . . . . . . . . . . . . . . . . . . . . . . . . 12 4 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 hw configuration of the STA2500D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 i/o supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 bluetooth controller v1.2 and v2.0 + edr features . . . . . . . . . . . . . . . . . 19 5.5 bluetooth controller v2.1 + edr (?lisbon?) . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 tx output power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 general specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 class 1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 low power clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.7 clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STA2500D contents doc id 16067 rev 1 3/57 6.8 clock request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.9 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10.2 some examples for the usage of the low power modes . . . . . . . . . . . . 30 6.10.3 deep sleep mode entry and wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.11 patch ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.12 download of sw parameter file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.13 bluetooth - wlan coexistence in collocat ed scenario . . . . . . . . . . . . . . . 38 6.13.1 algorithm 1: pta (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 38 6.13.2 algorithm 2: wlan master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13.3 algorithm 3: bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13.4 algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13.5 algorithm 5: alternating wireless medium access (awma) . . . . . . . . . . 40 7 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 the uart interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 the spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 the pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.4 the jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5 alternate i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.6 the i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 hci transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 h4 uart transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 enhanced h4 spi transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3 h4 spi transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.4 esco over hci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
list of tables STA2500D 4/57 doc id 16067 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. dc input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. dc output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. system clock supported frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. system clock overall specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 8. system clock, sine wave specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 9. system clock, digital clock dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 10. system clock, digital clock ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 11. low power clock specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 12. current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 13. the STA2500D pin list (functional and supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 14. configuration programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. i/o supply split diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 16. mbps receiver parameters - gfsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 17. mbps receiver parameters - /4-dqpsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 18. mbps receiver parameters - 8-dpsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 19. transmitter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. output power: class 1 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 21. output power: class 1 device pin configuration (depending on sw parameter download). 26 table 22. output power: class 1 device pin configuration (depending on sw parameter download). 26 table 23. use of the bt_clk_req_in and bt_clk_req_out signals in different modes. . . . . . 28 table 24. low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 25. wlan hw signal assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 26. spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 27. pcm interface parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 28. pcm interface timing (at pcm_clk = 2048 khz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 29. examples of bt_gpio pin programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 30. package markings legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 31. references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 33. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STA2500D list of figures doc id 16067 rev 1 5/57 list of figures figure 1. block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 2. pinout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. active high clock request input and output combined with uart or spi . . . . . . . . . . . . . . 28 figure 4. active low clock request input and output combined with uart . . . . . . . . . . . . . . . . . . . . 28 figure 5. active low clock request input and output combined with spi . . . . . . . . . . . . . . . . . . . . . . 28 figure 6. deep sleep mode entry and wake-up through h4 uart . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. entering deep sleep mode through enhanced h4 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. wake-up by the host through enhanced h4 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. wake-up by the bluetooth controller with data transmission to the host, through enhanced h4 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. deep sleep mode entry and wake-up through h4 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11. entering deep sleep mode, pending data on uart interface, through uart with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. wakeup by host through uart with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. pta diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14. wlan master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. bluetooth master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17. spi data transfer timing for data length of 8 bits and lsb first, full duplex . . . . . . . . . . . . . . 42 figure 18. spi setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. pcm (a-law, -law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 20. linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. multislot operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23. uart transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 24. lfbga48 (6x6x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 50 figure 25. package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
description STA2500D 6/57 doc id 16067 rev 1 1 description the STA2500D is a single chip bluetooth solution that is fully optimized for automotive applications such as telematics, navigation and portable navigation. power consumption levels are targeted at battery powered devices and single chip solution brings cost advantages. manufacturers can easily and quickly integrate the STA2500D on their product to enable a rapid time to market. STA2500D supports the bluetooth specification v2.1 + edr (?lisbon?) and is optimized in terms of rf performance and cost. the STA2500D is a rom-based solution targeted at applications requiring integration up to hci level. patch ram is available, enabling multiple patches/upgrades and fast time to volume. the STA2500D?s main interfaces are uart or spi for hci transport, pcm for voice and gpios for control purposes. the radio has been designed specifically for single chip requirements, for low power consumption and minimum bom count.
STA2500D quick reference data doc id 16067 rev 1 7/57 2 quick reference data bt_vio_x means bt_vio_a, bt_vio_b. bt_hvx means bt_hva, bt_hvd. (see also ta bl e 1 3 .) 2.1 absolute maximum ratings the absolute maximum rating (amr) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). 2.2 operating ranges operating ranges define the limits for functional operation and parametric characteristics of the device. functionality outside these limits is not implied. table 2. absolute maximum ratings symbol parameter min. max. unit bt_hvx core supply voltages -0.3 4.0 v bt_vio_a supply voltage i/o -0.3 4.0 v bt_vio_b supply voltage i/o (for the low power clock) -0.3 4.0 v bt_v in input voltage of any digital pin -0.3 4.0 v v ssdiff maximum voltage difference between different types of v ss pins. -0.3 0.3 v t stg storage temperature - 65 + 150 c table 3. operating ranges symbol parameter min. typ. max. unit bt_t amb operating ambient temperature -40 25 +85 c bt_hvx core supply voltages 2.65 2.75 2.85 v bt_vio_a i/o supply voltage 1.65 - 2.85 v bt_vio_b i/o supply voltage (for the low power clock) 1.17 - 2.85 v
quick reference data STA2500D 8/57 doc id 16067 rev 1 2.3 i/o specifications the i/os comply with the eia/jedec standard jesd8-b. 2.4 clock specifications the STA2500D supports, on the bt_ref_clk_in pin, the system clock both as a sine wave clock and as a digital clock. for configuration, see ta bl e 1 3 : pin bt_vdd_cld (e6). table 4. dc input specification symbol parameter min. typ. max. unit v il_bt low level input voltage -0.2 - 0.35 * bt_vio_x v v ih_bt high level input voltage 0.65 * bt_vio_x - (bt_vio_x + 0.2) and ( 2.85) v c in_bt input capacitance (1) 1. except for the system clock. 1-2.5pf r pu pull-up equivalent resistance (with v in = 0 v) 31 47 73 k r pd pull-down equiv. resistance (with v in = bt_vio_x) 29 50 100 k v hyst schmitt trigger hysteresis (at bt_vio_a = 1.8 v) except for bt_config1-3, bt_resetn, bt_wakeup 0.4 0.5 0.6 v v hyst schmitt trigger hysteresis (at bt_vio_x = 1.8 v) for bt_config1-3, bt_resetn, bt_wakeup, bt_lp_clk 0.223 - 0.314 v v hyst schmitt trigger hysteresis (at bt_vio_b = 1.3 v) 0.2 - 0.3 v table 5. dc output specification symbol parameter condition min. typ. max. unit v ol_bt low level output voltage i d = x (1) ma 1. x is the source/sink current under worst-case conditions according to th e drive capabilities (see section 3 ) --0.15v v oh_bt high level output voltage i d = x (1) ma bt_vio_x - 0.25 --v table 6. system clock supported frequencies symbol parameter values unit f in clock input frequency list 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6, 38.4 mhz table 7. system clock overall specifications symbol parameter min. typ. max. unit f intol tolerance on input frequency -20 - 20 ppm
STA2500D quick reference data doc id 16067 rev 1 9/57 table 8. system clock, sine wave specifications symbol parameter min. typ. max. unit v pp peak to peak voltage range 0.27 0.5 1.8 v n h total harmonic content of input signal - - -25 dbc z inre real part of parallel input impedance at pin 30 60 90 k z inim imaginary part of parallel input impedance at pin - 5 8 pf z idre real impedance discrepancy between active and non- active mode of clock input -- 7 k z idim imaginary impedance discrepancy between active and non-active mode of clock input --500ff phase noise @ 10 khz (1) ---126 dbc/hz 1. equivalent to max 10 ps time jitter (rms). table 9. system clock, digital clock dc specifications symbol parameter min. typ. max. unit v il low level input voltage -0.2 - 0.35 * bt_vdd_cld v v ih high level input voltage 0.65 * bt_vdd_cld - (bt_vdd_cld + 0.2) and ( 2.85) v c in input capacitance - 5 8 pf table 10. system clock, digital clock ac specifications symbol parameter min. typ. max. unit t rise 10% - 90% rise time - 1.5 6 ns t fall 90% - 10% fall time - 1.5 6 ns d cycle duty cycle 45 50 55 % - phase noise @ 10 khz (1) - - -121 dbc/hz 1. equivalent to max 15 ps time jitter (rms). table 11. low power clock specifications the low power clock pin is powered by connecting bt_vio_b to the wanted supply. symbol parameter min. typ. max. unit f in clock input frequencies 3.2, 32, 32.768 khz - duty cycle 30 - 70 % - tolerance on input frequency ? 250 - 250 ppm v il low level input voltage - - 0.35 * bt_vio_b v v ih high level input voltage 0.65 * bt_vio_b --v v hyst schmitt trigger hysteresis (bt_vio_b = 1.8 v) 0.4 0.5 0.6 v
quick reference data STA2500D 10/57 doc id 16067 rev 1 2.5 current consumption t amb = 25c, 13 mhz digital clock, 7 dbm output power for br packets, 3 dbm output power for edr packets. v hyst schmitt trigger hysteresis (bt_vio_b = 1.3 v) 0.2 0.3 0.4 v c in input capacitance 1 - 2.5 pf t rise 10% - 90% rise time (1) --1 s t fall 90% - 10% fall time (1) --1 s - total jitter (2) - - 250 ppm 1. the rise and fall time are not the most important parameters fo r the low power clock input due to the schmitt trigger logic. it is more important that the noise on the low power clock line remains substantially below the hysteresis in amplitude. 2. the total jitter is defined as the error that can appear on the actual frequency between two clock edges compared to the perfect frequency. due to this, the total jitter value must cont ain the jitter itself and the error due to the accuracy on the clock frequency. the lower the accuracy, the smaller the jitter is allowed to be. table 11. low power clock specifications (continued) the low power clock pin is powered by connecting bt_vio_b to the wanted supply. symbol parameter min. typ. max. unit table 12. current consumption (1) state typ. unit complete power down 1 a deep sleep mode 20 a functional sleep mode (2) 1.2 m a sniff mode (1.28 s, 2 attempts, 0 timeouts), combined with h4 uart deep sleep mode (see section 6.10.3) master mode slave mode 55 83 a a inquiry scan (1.28 seconds period), combined with h4 uart deep sleep mode (see section 6.10.3) 318 a hw page scan (1.28 seconds period), combined with h4 uart deep sleep mode (see section 6.10.3) 312 a hw inquiry and page scan (1.28 seconds period), combined with h4 uart deep sleep mode (see section 6.10.3) 591 a idle acl connection (master) 3.6 ma idle acl connection (slave) 8.2 ma active: audio (hv3) master (not sniffed) 11.7 ma active: audio (hv3) slave (sniff 1.28 s, 2 attempts, 0 timeouts) 10.6 ma active: data (dh1) master or slave (172.8 kbps asymmetrical in tx mode) (172.8 kbps symmetrical) 23 28.5 ma
STA2500D quick reference data doc id 16067 rev 1 11/57 active: data (dh5) master or slave (723.2 kbps asymmetrical in tx mode) (433.9 kbps symmetrical) 35.4 35.4 ma ma active: data (2-dh5) master or slave (869.7 kbps symmetrical) 35.4 ma active: data (3-dh5) master or sl ave (1306.9 kbps symmetrical) 35.4 ma active: audio esco (ev3), (64 kbps symmetrical t esco = 6) master mode slave mode 12 15 ma ma active: audio esco (2-ev3), (64 kbps symmetrical t esco = 12) master mode slave mode 7.8 11.7 ma ma active: audio esco (3-ev3), (64 kbps symmetrical t esco = 18) master mode slave mode 6.5 10.5 ma ma active: audio esco (ev5), (64 kbps symmetrical t esco = 36), master mode 8 ma active: audio esco (ev5), (64 kbps symmetrical t esco = 36), slave mode 11.9 ma active: audio esco (2-ev5), (64 kbps symmetrical t esco = 36), master mode 6.3 ma active: audio esco (3-ev5), (64 kbps symmetrical t esco = 36), master mode 5.75 ma 1. the power consumption (except for power safe modes i.e. complete power down and deep sleep mode) will rise (with approx. 200 a) if an analog sys tem clock is used instead of a digital clock. 2. in functional sleep mode, t he baseband clock is still running. table 12. current consumption (1) (continued) state typ. unit
block diagram and electrical schematic STA2500D 12/57 doc id 16067 rev 1 3 block diagram and electrical schematic figure 1. block diagram and electrical schematic filter receiver transmitter autocalibration demo- dulator modu- lator pll baseband core ebc arm7tdmi cpu wrapper ram rom amba periph. bus uart/ spi internal supply management timer interrupt pcm wlan bt_rfp bt_rfn bt_ref_clk_in rf pll fractional n control and register jtag i2c bt_hv[1:0] bt_vio_a bt_vio_b bt_gpio/jtag [4 :0] bt_lp_clk bt_host_wakeup / bt_spi_int bt_wakeup bt_resetn bt_uart/bt_spi [3 :0] bt_pcm [3 :0] bt_config [2 :0] bt_clk_req_in [1 :0] bt_clk_req_out [1:0] bt_gpio_0 bt_vdd[4:0] bt_test[1:0] bt_vdd_cld bt_af_prg bt_vss[5:0]
STA2500D pinout doc id 16067 rev 1 13/57 4 pinout figure 2. pinout (bottom view) 4.1 pin description and assignment ta bl e 1 3 shows the pin list of the STA2500D. in columns ?reset? and ?default after reset?, the ?pd/pu? shows the pads implementing an internal pull-down/up. the column ?reset? shows the state of the pins during hardware reset; the column ?default after reset? shows the state of the pins after the hardware reset state is left, but before any software parameter download. the column ?type? descri bes the pin directions: ? i for input (all inputs have a schmitt trigger function.) ? o for output ? i/o for input/output ? o/t for tri-state output jtag_tck gpio_0 gpio_3 7654321 a b c d e f g bt_resetn bt_ref_clk_in bt_lp_clk bt_host_wakeup /bt_spi_int bt_wakeup bt_uart_txd / bt_spi_do bt_uart_rxd / bt_spi_di bt_uart_cts / bt_spi_clk bt_vio_b bt_uart_rts / bt_spi_cs bt_pcm_sync bt_pcm_clk bt_pcm_a bt_pcm_b bt_gpio_9 bt_vssrf bt_gpio_10 bt_gpio_11 bt_gpio_16 bt_vssana bt_clk_req_in_1 bt_clk_req_in_2 bt_clk_req_out_1 bt_config_1 bt_config_3 bt_config_2 bt_rfp bt_rfn bt_hva bt_hvd bt_vdd_d bt_vio_a bt_vdd_cld bt_vdd_dsm bt_vdd_n bt_vdd_cl bt_vdd_rf bt_vssdig bt_vssdig bt_af_prg bt_vssana bt_vssana bt_test1 bt_test2 bt_clk_req_out_2 bt_vssrf bt_gpio_8 bt_gpio_0
pinout STA2500D 14/57 doc id 16067 rev 1 for the output pin the default drive capability is 2 ma, except for pin k3 (bt_gpio_11) and pin l3 (bt_gpio_8) where it is 8 ma such that when used for class 1, these 2 pins can be used for a switch control in a cheaper way. table 13. the STA2500D pin list (functional and supply) name pin # description type reset (1) default (2) after reset clock and reset pins bt_resetn d3 global reset - active low - - bt_ref_clk_in d6 reference clock input (3) i input input bt_lp_clk g3 low power clock input - - sw initiated low power mode bt_clk_req_out_1 c4 wake-up signal to host (active high or active low, depending on configuration pins) i/o (4) input pd/pu, depends on config output depends on config bt_clk_req_out_2 g7 wake-up signal to host. active low (spi mode only) input pu i/o depends on config bt_clk_req_in_1 e6 clock request in put (active high) input pd input pd bt_clk_req_in_2 g6 clock request input (active low) input pu input pu bt_host_wakeup/ bt_spi_int f7 wake-up signal to host or spi interrupt input pd output bt_wakeup c5 wake-up signal to bluetooth (active high) i/o input (5) input uart interface bt_uart_rxd/ bt_spi_di f5 uart receive data i/o (4) input pd input pd spi data in input pd bt_uart_txd/ bt_spi_do f6 uart transmit data output high spi data out input pd bt_uart_cts/ bt_spi_clk g4 uart clear to send input pu input pu spi clock input pd bt_uart_rts/ bt_spi_csn f4 uart request to send output low spi chip select input pu pcm interface bt_pcm_sync c2 pcm frame signal i/o (4) input pd input pd bt_pcm_clk d1 pcm clock signal bt_pcm_a d2 pcm data bt_pcm_b e1 pcm data jtag interface bt_gpio_9 b1 jtag_tdi or gpio - input pu (6) input pu (6)
STA2500D pinout doc id 16067 rev 1 15/57 bt_gpio_11 b2 jtag_tdo or gpio - input pd (6) input pd (6) bt_gpio_10 c1 jtag_tms or gpio i/o (4) input pd (6) input pd (6) bt_gpio_16 b3 jtag_ntrst (active low) or alternate function. - input pd (6) input pd (6) bt_gpio_8 c3 jtag_tck or gpio - input pd (6) input pd (6) general purpose input/output pins bt_gpio_0 d5 general purpose i/o i/o (4) input pd input pd configuration pins bt_config_1 e2 - - - bt_config_2 f1 configuration signal i input input bt_config_3 f2 - - - rf signals bt_rfp a3 differential rf port i/o -- bt_rfn a4 - - power supply bt_hva a7 power supply (connect to 2.75 v) - - - bt_hvd g1 bt_vio_a g5 1.65 v to 2.85 v i/os supply (7) -- - bt_vio_b f3 1.17 v to 2.85 v i/os supply (7) -- - bt_vdd_cld e7 system clock supply 1.65 v to 2.85 v (connect to bt_vio_a in case of a digital reference clock input, to bt_vssana in case of an analog reference clock input.) -- - bt_vssdig e3 digital ground - - - e4 bt_vssana b4 analog ground - - - b6 c6 bt_vssrf a2 rf ground - - - a5 bt_vdd_cl d7 internal supply decoupling/regulator output. need 220nf decoupling capacitor to bt_vssana. -- - table 13. the STA2500D pin list (functional and supply) (continued) name pin # description type reset (1) default (2) after reset
pinout STA2500D 16/57 doc id 16067 rev 1 4.2 hw configuration of the STA2500D by means of the three configuration pins, one can select the host interface (uart or spi) and clock request signal polarity to be used at startup. the available combinations of host interface and pr otocol are illustrated in ta bl e 1 4 (where ?1? = bt_vio_a and ?0? = bt_vssdig). additi onally, the polarity of the bt_clk_req signals can be programmed through the same pins. the polarity of the bt_clk_req_in and bt_clk_req_out signals is further described in section 6.8 . bt_vdd_d g2 internal supply decoupling/regulator output. need 220nf decoupling capacitor to bt_vssdig. -- - bt_vdd_dsm b7 internal supply decoupling/regulator output. need 220nf decoupling capacitor to bt_vssana. -- - bt_vdd_n c7 internal supply decoupling/regulator output. need 220nf decoupling capacitor to bt_vssana. -- - bt_vdd_rf a1 internal supply decoupling/regulator output. need 220nf decoupling capacitor to bt_vssrf. -- - other pins bt_test1 b5 test pin i/o input (8) input (8) bt_test2 a6 bt_af_prg e5 test pin (leave unconnected) (9) i/o open open 1. pin behaviour during hw reset (bt_resetn low). 2. pin behaviour immediately after hw reset and internal chip initialization, but before sw parameter download. 3. see also pin bt_vdd_cld in table 13 . 4. reconfigurable i/o pin.the functionality of these i/o s can be configured through softw are parameter download (see section 7.5 ). 5. should be strapped to bt_vssdig if not used. 6. jtag mode. 7. described in section 4.3 . 8. to be strapped to bt_vssana. 9. pin is st - reserved for test function and it must be soldered to an isolated pad (not connected to anything, just floating). table 13. the STA2500D pin list (functional and supply) (continued) name pin # description type reset (1) default (2) after reset
STA2500D pinout doc id 16067 rev 1 17/57 4.3 i/o supply the device STA2500D has two different i/o supplies: bt_vio_a and bt_vio_b. the two different pins may be potentially connected to separate dedicated voltage supplies in order to harmonize the digital levels to the platform. they are linked to different interfaces as described in ta bl e 1 5 . table 14. configuration programming bt_config_1 bt_config_2 bt_config_3 communication protocol bt_clk_req_out_1 bt_clk_req_out_2 0 1 0 h4 uart active high depending on sw config 0 1 1 h4 uart active low depending on sw config 1 1 0 reserved reserved reserved 1 1 1 reserved reserved reserved 1 0 0 reserved reserved reserved 1 0 1 enhanced h4 spi (1) active high active low 0 0 1 reserved reserved reserved 0 0 0 reserved reserved reserved 1. in order to get other spi modes, the host must send a specif ic configuration at start-up in addition of these configuration pins. table 15. i/o supply split diagram i/o supply name voltag e range [v] function associated pins bt_vio_a 1.65 - 2.85 configuration bt_config_1, bt_config_2, bt_config_3 control bt_wakeup bt_resetn bt_clk_req_out_1, bt_clk_req_out_2 gpio (jtag) bt_gpio_8 (jtag_tck), bt_gpio_9 (jtag_tdi), bt_gpio_10 (jtag_tms), bt_gpio_11 (jtag_tdo), bt_gpio_16 (jtag_ntrst) pcm bt_pcm_a, bt_pcm_b, bt_pcm_sync, bt_pcm_clk control bt_reg_ctrl uart (spi) bt_uart_rxd (spi_di), bt_uart_txd (spi_do), bt_uart_rts (spi_csn), bt_uart_cts (spi_clk), bt_host_wakeup (spi_int) control (gpio) bt_clk_r eq_in_1 (gpio_1), bt_c lk_req_in_2 (gpio_2) gpio bt_gpio_0 bt_vio_b 1.17 - 2.85 low - power clock bt_lp_clk
functional description STA2500D 18/57 doc id 16067 rev 1 5 functional description 5.1 transmitter the transmitter uses the serial transmit data from the bluetooth controller. the transmitter modulator converts this data into gfsk, /4-dqpsk or 8-dpsk modu lated i and q digital signals for respectively 1, 2 and 3 mbps transmission speed. these signals are then converted to analog signals that are low pass filtered before up-conversion. the carrier frequency drift is limited by a closed loop pll. 5.2 receiver the STA2500D implements a low-if receiver for bluetooth modulated input signals. the radio signal is taken from a balanced rf input and amplified by an lna. the mixers are driven by two quadrature lo signals, which are locally generated from a vco signal running at twice the frequency. the i and q mixer output signals are band pass filtered by a poly- phase filter for channel filtering and image rejection. the output of the band pass filter is amplified by a vga to the optimal input range for the a/d converter. further channel filtering is done in the digital part. the digital part demodulates the gfsk, /4-dqpsk or 8-dpsk coded bit stream by evaluating the phase information. rssi data is extracted. overall automatic gain amplification in the receive path is controlled di gitally. the rc time constants for the analog filters are automatically calibrated on chip. 5.3 pll the on-chip vco is part of a pll. the tank re sonator circuitry for the vco is completely integrated without need of external components. variations in the vco centre frequency are calibrated out automatically.
STA2500D functional description doc id 16067 rev 1 19/57 5.4 bluetooth controller v1.2 and v2.0 + edr features the bluetooth controller is backward compatible with the bluetooth specification v1.2 [] and v2.0 + edr []. here below is a list with th e main features of those specifications: adaptive frequency hopping (afh): hopping kernel, channel assessment as master and as slave fast connection: interlaced scan for page and inquiry scan, answer fhs at first reception, rssi used to limit range extended sco (esco) links: supports ev3, ev4 and ev5 packets channel quality driven da ta rate change (cqddr) qos flush synchronization: bt clocks are available at hci level for synchronization of parallel applications on different slaves l2cap flow & error control lmp sco handling 2 mbps packet types ? acl: 2-dh1, 2-dh3, 2-dh5 ? esco: 2-ev3, 2-ev5 3 mbps packet types ? acl: 3-dh1, 3-dh3, 3-dh5 ? esco: 3-ev3, 3-ev5 5.5 bluetooth controller v2.1 + edr (?lisbon?) encryption pause/resume (epr) extended inquiry response (eir) link supervision time out (lsto) secure simple pairing sniff subrating quality of service (qos) ? packet boundary flag ? erroneous data delivery 5.6 processor and memory arm7tdmi on chip ram, includi ng provision for patches on chip rom, preloaded with sw up to hci
functional description STA2500D 20/57 doc id 16067 rev 1 5.7 tx output power control the STA2500D supports output power control with advanced features: basic feature: ? with the standard tx powe r control algorith m enabled, the st a2500d will adapt its output power when a remote bt device supports the rssi feature; this allows the remote device to measure the link strength and to request the STA2500D to decrease/increase its output power. in case the remote device does not support the rssi feature, the STA2500D will use its ?default? output power level. advanced features, available via specific hci commands: ? enhanced power control feature: allows the STA2500D to decrease autonomously its output power until the remote bt device, supporting the rssi feature, requests to increase the output power.
STA2500D general specification doc id 16067 rev 1 21/57 6 general specification all the values are provided according to the bluetooth specification v2.1 + edr (?lisbon?) unless otherwise specified. the below values ar e preliminary and will be updated in the next version of this datasheet. 6.1 receiver all specifications below are given at device pi n level and with the conditions as specified. parameters are given for each of the 3 modulation types supported. typical is defined at t amb = 25 c, bt_hv = 2.75 v. minimum and maximum are worst cases over corner lots and temperature. parameters are given at device pin, except for receiver interferers measured at antenna with a filter having a typical attenuation of 2.3 db. table 16. mbps receiver parameters - gfsk symbol parameter test condition min. typ. max. unit rfin input frequency range - 2402 - 2480 mhz rxsensc receiver sensitivity (clean transmitter) @ ber 0.1% - -88 -86 dbm rxsensd receiver sensitivity (dirty transmitter) @ ber 0.1% - -87 -84 dbm rxmax maximum useable input signal level @ ber 0.1% - 10 15 dbm receiver blocking performance @ ber 0. 1% on channel 58 (without filter) - signal in gsm band 900 mhz (824 mhz to 960 mhz) @ input signal strength = -67 dbm --15-dbm - signal in gsm band 1800 mhz (1805 mhz to 1990 mhz) @ input signal strength = -67 dbm - -2.5 - dbm - signal in wcdma band (2010 mhz to 2170 mhz) @ input signal strength = -67 dbm --1.5- dbm receiver interferer performance @ ber 0.1% c/i co-channel co-channel interference @ input signal strength = -60 dbm -9.511db c/i 1mhz adjacent (1 mhz) interference @ input signal strength = -60 dbm --90db c/i +2mhz adjacent (+2 mhz) interference @ input signal strength = -60 dbm --40-30db c/i -2mhz adjacent (-2 mhz) interference @ input signal strength = -67 dbm --26-9db c/i +3mhz adjacent (+3 mhz) interference @ input signal strength = -67 dbm - -46.5 -40 db
general specification STA2500D 22/57 doc id 16067 rev 1 typical is defined at t amb = 25 c, bt_hv = 2.75 v. minimum and maximum are worst cases over corner lots and temperature. parameters are given at device pin, except for receiver interferers measured at antenna with a filter having a typical attenuation of 2.3 db. c/i -3mhz adjacent (-3 mhz) interference @ input signal strength = -67 dbm --43-20db c/i 4mhz adjacent ( 4 mhz) interference @ input signal strength = -67 dbm --48-40db receiver inter-modulation imd inter-modulation measured as defined in bt test specification []. -39 -32 = dbm table 16. mbps receiver parameters - gfsk (continued) symbol parameter test condition min. typ. max. unit table 17. mbps receiver parameters - /4-dqpsk symbol parameter test condition min. typ. max. unit rfin input frequency range = 2402 2480 mhz rxsensc receiver sensitivity (clean transmitter) @ ber 0.01% - -87 -85 dbm rxsensd receiver sensitivity (dirty transmitter) @ ber 0.01% - -86.5 -84.5 dbm rxmax maximum useable input signal level @ ber 0.1% -15 -9 - dbm receiver blocking performance @ ber 0.1% on channel 58 (without filter) - signal in gsm band 900 mhz (824 mhz to 960 mhz) @ input signal strength = -67 dbm - -15.5 - dbm - signal in gsm band 1800 mhz (1805 mhz to 1990 mhz) @ input signal strength = -67 dbm - -3.5 - dbm - signal in wcdma band (2010 mhz to 2170 mhz) @ input signal strength = -67 dbm - -2.5 - dbm receiver interferer performance @ ber 0.1% c/i co-channel co-channel interference @ input signal strength = -60 dbm -1113db c/i 1mhz adjacent ( 1 mhz) interference @ input signal strength = -60 dbm - -11.5 0 db c/i +2mhz adjacent (+2 mhz) interference @ input signal strength = -60 dbm - -40 -30 db c/i -2mhz adjacent (-2 mhz) interference @ input signal strength = -67 dbm --20-7db c/i +3mhz adjacent (+3 mhz) interference @ input signal strength = -67 dbm - -48.5 -40 db
STA2500D general specification doc id 16067 rev 1 23/57 typical is defined at t amb = 25 c, bt_hv = 2.75 v. minimum and maximum are worst cases over corner lots and temperature. parameters are given at device pin, except for receiver interferers measured at antenna with a filter having a typical attenuation of 2.3 db. c/i -3mhz adjacent (-3 mhz) interference @ input signal strength = -67 dbm --47-20db c/i 4mhz adjacent ( 4 mhz) interference @ input signal strength = -67 dbm --48-40db table 17. mbps receiver parameters - /4-dqpsk (continued) symbol parameter test condition min. typ. max. unit table 18. mbps receiver parameters - 8-dpsk symbol parameter test condition min. typ. max. unit rfin input frequency range - 2402 - 2480 mhz rxsensc receiver sensitivity (clean transmitter) @ ber 0.01% - -79.5 -77.5 dbm rxsensd receiver sensitivity (dirty transmitter) @ ber 0.01% - -77 -74.5 dbm rxmax maximum useable input signal level @ ber 0.1% -20 -15 - dbm receiver blocking performance @ ber 0.1% on channel 58 (without filter) - signal in gsm band 900 mhz (824 mhz to 960 mhz) @ input signal strength = -67 dbm --20-dbm - signal in gsm band 1800 mhz (1805 mhz to 1990 mhz) @ input signal strength = -67 dbm - -14.5 - dbm - signal in wcdma band (2010 mhz to 2170 mhz) @ input signal strength = -67 dbm --14-dbm receiver interferer performance @ ber 0.1% c/i co-channel co-channel interference @ input signal strength = -60 dbm -1921db c/i 1mhz adjacent ( 1 mhz) interference @ input signal strength = -60 dbm --45db c/i +2mhz adjacent (+2 mh z) interference @ input signal strength = -60 dbm --37-25db c/i -2mhz adjacent (-2 mhz) interference @ input signal strength = -67 dbm --120db c/i +3mhz adjacent (+3 mh z) interference @ input signal strength = -67 dbm --46-33db c/i -3mhz adjacent (-3 mhz) interference @ input signal strength = -67 dbm --40-13db c/i 4mhz adjacent ( 4 mhz) interference @ input signal strength = -67 dbm --43-33db
general specification STA2500D 24/57 doc id 16067 rev 1 6.2 transmitter unless otherwise stated, typical is defined at t amb = 25 c, bt_hv = 2.75 v. minimum and maximum are worst cases over corner lots and temperature. parameters are given at device pin, except for in-band spurious measured at antenna. table 19. transmitter parameters symbol parameter test condition min. typ. max. unit rfout output frequency range - 2402 - 2480 mhz rf transmit power txpout (gfsk) maximum output power (1) @ 2402 - 2480 mhz @ 25 c 6 8 10 dbm txpout (gfsk) maximum output power (1) @ 2402 - 2480 mhz @ worst cases over corner lots and temperature 4.5 8 10.5 dbm txpout (gfsk) minimum output power @ 2402 - 2480 mhz -52.5 -47.5 -42.5 dbm txpout ( /4-dqpsk) maximum output power (1) (2) @ 2402 - 2480 mhz @ 25 c 3.5 6 8 dbm txpout ( /4-dqpsk) minimum output power (2) @ 2402 - 2480 mhz -43.5 -38.5 -33.5 dbm txpoutrel ( /4-dqpsk) relative transmit power (3) @ 2402 - 2480 mhz - -0.2 - db txpout (8-dpsk) maximum output power (1) (2) @ 2402 - 2480 mhz @ 25 c 3.5 6 8 dbm txpout (8-dpsk) minimum output power (2) @ 2402 - 2480 mhz -43.5 -38.5 -33.5 dbm txpoutrel (8-dpsk) relative transmit power (3) @ 2402 - 2480 mhz - -0.2 - db in-band spurious emission (4) fcc fcc?s 20 db bw - 900 930 950 khz acp_2 channel offset = 2 mhz - - -43.5 -20 dbm acp_3 channel offset = -3 mhz - - -52.5 -40 dbm acp_4 channel offset 4 mhz - - -54.5 -40 dbm edr_ibs_1 channel offset = 1 mhz (2 and 3 mbps) - - -33.5 -26 db edr_ibs_2 channel offset = 2 mhz (2 and 3 mbps) ---31.5-20 dbm edr_ibs_3 channel offset = 3 mhz (2 and 3 mbps) ---45-40 dbm edr_ibs_4 channel offset = 4 mhz (2 and 3 mbps) ---50-40 dbm
STA2500D general specification doc id 16067 rev 1 25/57 initial carrier frequency tolerance (for an exact reference) (5) f |f_tx-f0| - - 0 - khz carrier frequency stability (6) | f_s| carrier frequency stability - - 3.2 10 khz carrier frequency drift (7) | f_p1| one slot packet - - 12 25 khz | f_p3| three slots packet - - 14 40 khz | f_p5| five slots packet - - 14 40 khz carrier frequency drift rate (7) | f/50us| frequency drift rate - - 8/50 20/50 khz/s modulation accuracy (6) (7) (8) f1avg maximum modulation - 140 163 175 khz f2max minimum modulation - 115 135 - khz f1avg/ f2avg -0.80.9- - 2-dh5 rms devm - - 8 20 % - 2-dh5 99% devm - - - 30 % - 2-dh5 peak devm - - 21 35 % - 3-dh5 rms devm - - 8 13 % - 3-dh5 99% devm - - - 20 % - 3-dh5 peak devm - - 21 25 % tx out of band emission e850 emission in gsm band 850 mhz bw = 200 khz (7) (9) (10) --79-76dbm e900 emission in gsm band 900 mhz bw = 200 khz (7) (9) (10) --79-76dbm e1500 emission in gps band bw = 200 khz (7) (9) (10) --85-84dbm e1800 emission in gsm band 1800 mhz bw = 200 khz (7) (9) (10) --87-84dbm e1900 emission in gsm band 1900 mhz bw = 200 khz (7) (9) (10) --87-84dbm ewcdma emission in wcdma band bw = 3.8 mhz (7) (9) (10) --78-75dbm 1. lower transmit power (i.e. class 2) can be obtained by prog ramming the radio init power table via software parameter download or an hci command. 2. power of gfsk part. 3. relative power of edr part compared to the gfsk part. 4. at antenna with maximum output power, filter attenuation of 2.3 db. 5. phase noise will add maximum [-10 khz;10 khz] for worst case clock 270 mvpp at 13 mhz. 6. worst case clock 270 mvpp at 13 mhz. measuremen t according to edr rf test spec v2.0.e.3 []. 7. with maximum output power (br or edr). 8. measured on reference design stlc2555_rev1.1 following ebom and layout recommendations. 9. measurement bandwidth. 10. transmitting dh5 packets. table 19. transmitter parameters (continued) symbol parameter test condition min. typ. max. unit
general specification STA2500D 26/57 doc id 16067 rev 1 6.3 class 1 operation the STA2500D supports operation at class 1 output power levels with the use of an external pa. the operation of the external pa and antenna switch are controlled by the following signals: if class 1 functionality is enabled through sw parameter download, then these 6 control signals are available on the pins as indicated in ta b l e 2 1 and ta b l e 2 2 . configuration 2 allows to deploy the st a2500d in class 1 mode, still maintaining the necessary control signals to coexist and cooperate with a wlan transceiver. the handshake between the STA2500D and a wlan device happens in this case through other bt_gpio pins. 6.4 power-up the bt_resetn pin should be active while powering up bt_vdd_hv and should stay active at least two cycles of the low power clock (bt_lp_clk) after power-up is completed. the time between the STA2500D making bt _clk_req_out_x active and the platform providing a stable clock should maximally be 15 ms. table 20. output power: class 1 control signals control signal name function paen pa enable (active during tx slot) pa_val0 bit 0 of the power level delivered by the pa pa_val1 bit 1 of the power level delivered by the pa rxen lna enable (if present) antsw control of the antenna switch edr_mode indication to pa whether tx is edr or br table 21. output power: class 1 device pin configuration (depending on sw parameter download) function sw configuration 1 sw configuration 2 paen bt_host_wakeup bt_gpio_16 pa_val0 bt_gpio_0 bt_gpio_10 pa_val1 bt_clk_req_in_1 bt_gpio_9 rxen bt_clk_req_in_2 bt_gpio_8 antsw (bt_gpio_11) bt_gpio_11 table 22. output power: class 1 device pin configuration (depending on sw parameter download) function sw configuration a sw configuration b sw configuration c edr_mode bt_clk_req_out_1 bt_clk_req_out_2 not available on a pin
STA2500D general specification doc id 16067 rev 1 27/57 6.5 system clock the STA2500D works with a sine wave or digital clock provided on the bt_ref_clk_in pin. detailed specifications are found in section 2.4 . 6.6 low power clock the low power clock is used by the bluetooth controller as reference clock during the low power modes. it requires an accuracy of + 250 ppm. the STA2500D requires a digital clock to be provided on the bt_lp_clk pin, with frequencies of 3.2 khz, 32 khz and 32.768 khz. after power-up, the low power clock must be available before the reset is released. it must remain active all the time until the STA2500D is powered off. 6.7 clock detection an integrated automatic detection algorithm detects the system and low power clock frequencies after a hardware reset. the steps in the clock detection routine are: identification of the system clock frequen cy (9.6 mhz, 10 mhz, 13 mhz, 16 mhz, 16.8mhz, 19.2 mhz, 26 mhz, 33.6 mhz or 38.4 mhz) identification of the low power clock (3.2 khz, 32.768 khz or 32 khz). 6.8 clock request signals to allow minimum power consumption, a clock request feature is available so that the system clock (bt_ref_clk_in) can be stopped when not needed by the bluetooth system. the clock request signal can be acti ve high or active low, and the STA2500D supports internal propagation of clock reques t signal coming from another device in the system. different configurations as described below are supported immediately after reset and in all bluetooth operation modes, provided that bt_vio_a is available. the clock request functionality is based on four different signals: bt_clk_req_out_1, bt_clk_req_out_2, bt_clk_req_in_1, bt_clk_req_in_2, with the following function: bt_clk_req_out_1: active low or high clock request, depending on hw configuration pins (table ). support for either push-pull or open drain output. bt_clk_req_out_2: active low clock request, only used in combination with spi mode. support for either push-pull or open drain output. bt_clk_req_in_1: active high clock reques t input from an other device, depending on hw configuration pin. bt_clk_req_in_2: active low clock request input from an other device. the following modes are supported: active high clock request input and output combined with uart or spi:
general specification STA2500D 28/57 doc id 16067 rev 1 figure 3. active high clock request input and output combined with uart or spi active low clock request input and output combined with uart: figure 4. active low clock request input and output combined with uart active low clock request input and output combined with spi: figure 5. active low clock request input and output combined with spi the pins which are ?not used? are available for alternate functions as described in section 7.5 . bt_clk_req_out_1 or bt_clk_req_in_1 internal bt clk request bt_clk_req_in_2 (*) (*) bt_clk_req_in_1 and bt_clk_req_in_2 ar e used unless one or both are re-programmed as alternate function(s) via parameter fi le (*) not bt_clk_req_out_1 and bt_clk_req_in_1 internal bt clk request bt_clk_req_in_2 (*) bt_clk_req_in_1 and bt_clk_req_in_2 ar e used unless one or both are re-programmed as alternate function(s) via parameter fi le (*) (*) not bt_clk_req_out_2 and bt_clk_req_in_1 internal bt clk request bt_clk_req_in_2 (*) bt_clk_req_in_1 and bt_clk_req_in_2 ar e used unless one or both are re-programmed as alternate function(s) via parameter fi le (*) (*) not table 23. use of the bt_clk_req_in and bt_clk_req_out signals in different modes bt_config_1 bt_config_2 bt_config_3 protocol bt_clk_ req_in_1 bt_clk_ req_in_2 bt_clk_r eq_out_1 bt_clk_r eq_out_2 010h4 uart active high (1) active low (1) active high not used 011h4 uart active low (1) active low (1) active low not used 101 enhanced h4 spi active high active low active high active low 1. bt_clk_req_in_1 and bt_clk_req_in_2 are used in the configuration logic, unless one or both i/os re- programmed as alternate function(s) via the parameter file.
STA2500D general specification doc id 16067 rev 1 29/57 6.9 interrupts the user can program the bt_gpios as external interrupt sources. 6.10 low power modes 6.10.1 overview to save power, three low power modes are supported as described in ta bl e 2 4 . depending of the bluetooth and of the host's activity, the STA2500D decides to use sleep mode or deep sleep mode. note however that the deep sleep mode must first be activated via sw parameter download or an hci comma nd prior to any possibility to use it as the default configuration is only sleep mode. complete power down is entered only after an explicit command from the host. table 24. low power modes low power mode description sleep mode the STA2500D: ? accepts hci commands from the host. ? supports all types of bluetooth links. ? can transfer data over bluetooth links. ? dynamically switches between sleep and active mode when needed. ? the system clock is still acti ve in part of the design. ? parts of the chip are dynamically powered off depending on the bluetooth activity. deep sleep mode the STA2500D: ? does not accept hci commands from the host. ? supports page and inquiry scans. ? supports bluetooth links that are in sniff or sniff subrating. ? dynamically switches between deep sleep and active mode during bluetooth activity. the deep sleep mode entry is initiated by the host, the STA2500D acknowledges or not. the wake-up mechanism must be enabled by a sw parameter download before it can be us ed. more details in section 6.10.3. ? the system clock is not active in any part of the design. ? parts of the chip are dynamically powered off depending on the bluetooth activity. complete power down the STA2500D is effectively powered down: ? no bluetooth activity is supported. ? the hci interface is shut down. ? the system clock is not active in any part of the design. ? most parts of the chip are completely powered off. ? ram content is not maintained (initialisation is required at wake-up). ? some pins (uart/spi i/os and the 4 clock request signals and bt_gpio_16) keep their previous configuration (input or output, pull behaviour) during completed power down. ? the complete power down entry is initiated by an hci command followed by a deep sleep command, this in order to ens ure a smooth transition from active to complete power down state. in order to go out of this mode, either a hw reset or bt_wakeup = ?1? is needed.
general specification STA2500D 30/57 doc id 16067 rev 1 6.10.2 some examples for the usage of the low power modes sniff or sniff subrating the STA2500D is in active mode with a bluetooth connection. once the transmission is concluded, sniff or sniff subrating is programm ed. when one of these two states is entered, the STA2500D goes into sleep mode. after that, the host may decide to place the STA2500D in deep sleep mode as described in section 6.10.3 . the deep sleep mode allows for lower power consumption. when the STA2500D needs to send or receive a packet (e.g. at t sniff or at the beacon instant), the STA2500D requests the system clock and enters active mode for the needed transmission/reception. immediately afterwards, the STA2500D will go back to deep sleep mode. if some hci transmissi on is needed, the uart/spi link will be reactivated, using one of the four ways explained in section 6.10.3 and the STA2500D will move from de ep sleep mode to sleep mode. inquiry/page scan when only inquiry scan or page scan is en abled, the STA2500D will go in sleep mode or deep sleep mode outside the receiver activity. the selection between sleep mode and deep sleep mode depends on the uart/spi activity as in sniff or sniff subrating. no connection if the host allows deep sl eep mode (as described in section 6.10.3 ) and there is no activity, then the STA2500D puts itself in deep sleep mode. it is possible to exit the deep sleep mode by using one of the four methods explained in section 6.10.3 . in this deep sleep mode (no connection), the host can also decide to put the STA2500D in complete power down to further reduce the powe r consumption. in this case some part of the STA2500D will be completely powered off. the request to quit the complete power down is done either by putting the bt_wakeup signal to ?1? or with an hw reset. active link when there is an active link ((e)sco or ac l), the bluetooth contro ller will not go in deep sleep mode and not in complete power down. bu t the bluetooth controlle r is made in such a way that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in sleep mode. 6.10.3 deep sleep mode entry and wake-up during periods of no activity on the bluetooth and on the host side, the chip can be placed in deep sleep mode. four ways to initiate deep sleep mode and to wake up are supported (selection is done through software parameter do wnload): they are respectively based on a uart interface in the first case, an spi interface in the second case and third case, while either uart or spi interfaces can be used in the fourth case that is based on an handshake mechanism. deep sleep mode entry and wake up through h4 uart it requires bt_clk_req_out_1, bt_uart_rxd and bt_uart_rts. the bt_uart_rxd is used as wake-up signal from the host, the bt_clk_req_out_1 requires the clock from the host and the bt_uart_rts indicates when the STA2500D is
STA2500D general specification doc id 16067 rev 1 31/57 available. in this mode, the break function (bt_uart_rxd is low for more than 1 word) is used to distinguish between normal operation and low power mode usage. deep sleep mode entry the host tells the STA2500D that it can go in deep sleep mode power by forcing the bt_uart_rxd of the STA2500D to '0' for more than 1 word. the STA2500D decides to go in deep sleep mode, or not, depending on its scheduled activity and on the number of events or data packets to be sent to the host. in case it decides to go in deep sleep mode, it signals it by forcing bt_uart_rts high; then it asserts bt_clk_req_out_1 low to tell the host that it does not need the clock anymore. the STA2500D cannot go in deep sleep mode by itself. this is a logical consequence of the fact that the system clock is needed to receive characters on the uart. note that when the system is in deep sleep mode, the uart is closed. deep sleep mode wake-up the wake-up procedure can be initiated by the host or by the STA2500D. in the latter case, it can be with or without communication, depending if there are data to be transmitted to the host. 1. wake-up initiated by the host the host sets the bt_uart_rxd pin of the STA2500D to '1'. then the STA2500D asks the host to restart the system clock by setting bt_clk_req_out_1 to '1'. when the clock is available, the STA2500D confirms it is awake by releasing bt_uart_rts to '0'. 2. autonomous wake-up with uart communication (i.e. initiated by the STA2500D) the STA2500D first asks the host to restart the system clock by setting bt_clk_req_out_1 to '1'. when the clock is available, the STA2500D sets bt_uart_rts low, and then the host can give confirmation by releasing the bt_uart_rxd of the STA2500D. another possibility is that th e STA2500D sets bt_host_wake up to ?1? to request the host attention. then the host can give confirmation by releasing the bt_uart_rxd of the STA2500D and the STA2500D sets bt_uart_rts low. the choice between the two possibilities is selected by a software parameter. 3. autonomous wake-up without uart communication (i.e. initiated by the STA2500D) the STA2500D asks the host to restart the system clock by setting bt_clk_req_out_1 to '1'.
general specification STA2500D 32/57 doc id 16067 rev 1 figure 6. deep sleep mode entry and wake-up through h4 uart deep sleep mode entry and wake-up through enhanced h4 spi in this case no additional signals are needed to control the deep sleep mode and the wake- up mechanism except for bt_clk_req_out_x (bt_clk_req_out_1 for active high polarity and bt_ clk_req_out_2 for active low polarity). the enhanced h4 prot ocol makes use of three mess ages: sleep, wakeup and woken. more details on the enhanced h4 protocol can be found in section 8.2 . deep sleep mode entry entering deep sleep mode can only be initiated by the host sending a sleep message to the bluetooth controller. if that one accepts it, the device enters deep sleep mode: consequently the bluetooth controller de-asserts bt_clk_req_out_x and internally gates the system clock. this is illustrated in figure 7 . if there is still pending activity at the bluetooth side on the air, the bluetooth controller does not immediately enter deep sle ep mode and therefore bt_clk_req_out_x stays 'active' during this period: however the bluetooth controlle r will go in deep sleep mode at the end of the air activity. if there is pending data to be transferred to the host, the bluetooth controller will request a data transfer: however the blueto oth controller will go in deep sleep mode at the end of the data transfer. deep sleep mode wake-up wake-up can be requested by the host or autonomously by the bluetooth controller. in the latter case, it can be with or without communication on the interface (i.e. during page scan, there is no data to transfer to the host). 1. wake-up initiated by the host in the case of a wake-up by the host, it sends a wakeup command and waits for a woken response before starting the data exchange. of course the bluetooth controller must first request the system clock through bt_clk_req_out_x. it should be noted that the wakeup messa ge is decoded in the bluetooth controller's active sleep mode mode uart off bb uart on host_wakeup =? 1? or ? 0? ?a? : active high/low ?p? : passive low/high bt controller : clk_req_out_1 =? p? active sleep mode bb hos t: uart_ rxd=? 0? bt controller : uart_ rts= ?1? uart off hos t: uart_ rxd=? 1? bt controller : uart_ rts= ?0? or host_wakeup=?1? bt controller : clk_req_out_1 =? a? host_wakeup =? 0? hos t: uart_ rxd=? 1? and bt controller : clk_req_out_1 =? a? and uart_ rts= ?0? active sleep mode deep sleep uart off bb uart on host_wakeup =? 1? or ? 0? bt_clk_req_out_1 = bt controller : bt_clk_req_out_1 =? p? active sleep mode bb hos t: bt_ua rt_rxd =? 0? bt controller : bt_ua rt_rts=? 1? uart off hos t: bt_ua rt_rxd =? 1? bt controller : bt_ua rt_rts = ?0? or bt_host_wakeup= ?1? bt controller : bt_clk_req_out_1 =? a? host_wakeup =? 0? hos t: bt_ua rt_rxd=? 1? and bt controller: bt_clk_req_out_1 =? a? and bt_ua rt_rts=? 0?
STA2500D general specification doc id 16067 rev 1 33/57 spi hw block even before the system cloc k is available. this block will generate an interrupt, allowing the blue tooth controller to reply wit h a woken message. this is illustrated in figure 8 . 2. autonomous wake-up with communication (i.e. initiated by the STA2500D) in the case of an autonomous wake-up with data transmission, the bluetooth controller sets bt_spi_int high to request the spi interface and waits for bt_spi_csn going low, indicating the spi transaction starts. of course the bluetooth controller must first request the system clock through bt_clk_req_out_x before being able to start the process. this is illustrated in figure 9 . note that the bluetooth controller goes back to deep sleep mode at the end of the data transfer. 3. autonomous wake-up without communication (i.e. initiated by the STA2500D) for autonomous wake-up without spi communication, the STA2500D only asserts bt_clk_req_out_x to get the system clock. figure 7. entering deep sleep mode through enhanced h4 spi figure 8. wake-up by the host through enhanced h4 spi ref_clk _in clk _req_out _1 spi_clk 1 2 3 spi_di spi_do spi_int 4 spi_csn sleep ref_clk _in clk _req_out _1 spi_clk 1 2 3 spi_di spi_do spi_int 4 spi_csn wakeup 5 woken
general specification STA2500D 34/57 doc id 16067 rev 1 figure 9. wake-up by the bluetooth controller with data transmission to the host, through enhanced h4 spi deep sleep mode entry and wake-up through h4 spi it requires bt_clk_req_out_x (bt_clk_req_out_1 for active high polarity and bt_clk_req_out_2 for active low polarity), bt_wakeup and bt_spi_int. the bt_wakeup is used as wake-up signal from the host, the bt_clk_req_out_x requires the clock from the host and bt_spi_int is used as a wake-up signal from the bluetooth controller. deep sleep mode entry the host tells the STA2500D that it can go in deep sleep mode by forcing the bt_wakeup of the STA2500D to ?0?. the st a2500d decides to go in deep sleep mode, or not, depending on its scheduled activity and on the number of events or data packets to be sent to the host. in case it decides to go in deep sleep mode, it asserts bt_clk_req_out_x ?inactive? to tell the host that it does not need the clock anymore. the STA2500D cannot go in deep sleep mode by itself. note that the host cannot force bt_wakeup to ?0? before the end of a write o peration from the host, this in order to allow correct decoding of the message by the bluetooth controller. deep sleep mode wake-up the wake-up procedure can be initiated by the host or by the STA2500D. in the latter case, it can be with or without communication, depending if there are data to be transmitted to the host. 1. wake-up initiated by the host the host sets the bt_wakeup pin of the STA2500D to ?1?. then the STA2500D asks the host to restart the system clock by se tting bt_clk_req_out_x to ?active?. when the clock is available and stable, the host can use bt_spi_csn to start an spi transaction if needed (there is a programmable minimum delay between the assertion of bt_clk_req_out_x and the moment the host can assert bt_spi_csn). 2. autonomous wake-up with spi communicat ion (i.e. initiated by the STA2500D) the STA2500D first asks the host to restart the system clock by setting bt_clk_req_out_x to ?active?. when the clock is available, the STA2500D sets bt_spi_int high to request the spi interface to the host and waits for bt_spi_csn going low, indicating the spi transaction starts. 3. autonomous wake-up without spi communication (i.e. initiated by the STA2500D) the STA2500D asks the host to restart the system clock by setting bt_clk_req_out_x to ?active?. ref_clk _in clk _req _out_1 spi_clk 1 2 3 spi_di spi_do spi_int 4 spi_csn data 5
STA2500D general specification doc id 16067 rev 1 35/57 figure 10. deep sleep mode entry and wake-up through h4 spi deep sleep mode entry and wake-up through h4 uart or h4 spi with handshake this method is supported by both h4 uart and h4 spi. the descripti on below is for h4 uart. it requires bt_clk_req_out_1, bt_wakeup and bt_host_wakeup. the bt_wakeup is used as wake-up signal from the host, the bt_clk_req_out_1 requires the clock from the host and bt_host_wakeup is used as a wake-up signal from the bluetooth controller. deep sleep mode entry the host tells the STA2500D that it can go in deep sleep mode by forcing the bt_wakeup of the STA2500D to ?0?. the st a2500d decides to go in deep sleep mode, or not, depending on its scheduled activity and on the number of events or data packets to be sent to the host. in case it decides to go in deep sleep mode, it asserts bt_clk_req_out_1 low to tell the host that it does not need the clock anymore. on the contrary, if it still wants the interfac e active for up-transmission, it keeps bt_host_wakeup to ?1? as long as needed before de-asserting bt_clk_req_out_1. this is illustrated in figure 11 . deep sleep mode wake-up the wake-up procedure can be initiated by the host or by the STA2500D. in the latter case, it can be with or without communication, depending if there are data to be transmitted to the host. 1. wake-up initiated by the host the host sets the bt_wakeup pin of the STA2500D to ?1?. then the STA2500D asks the host to restart the system clock by setting bt_clk_req_out_1 to ?1?. when the clock is available and stable, the STA2500D puts bt_uart_rts low to allow communication. in case the STA2500D wants to send events to the host, it then puts active sleep mode mode spi off bb spi on host_wakeup =? 1? or ? 0? clk_req_out_1 = ? a? : active high/low ? p? : passive low/high bt controller : clk_req_out_1 =? p? active sleep mode bb hos t: bt_wakeup=?0? spi off hos t: bt_wakeup=?1? or bt controller : spi_int=? 1? bt controller : clk_req_out_1 =? a? host_wakeup =? 0? hos t: bt_wakeup=?1? and bt controller : clk_req_out_1 =? a ? active sleep mode deep sleep mode spi off bb spi on host_wakeup =? 1? or ? 0? clk_req_out_1 = ? a? : active high/low ? p? : passive low/high bt controller :bt_clk_ req_out_1=? p? active sleep mode bb host: bt_wakeup=?0? spi off hos t: bt_wakeup=?1? or bt controller : bt_spi_int =? 1 ? bt controller : bt_clk_ req_out_1=?a? host_wakeup =? 0? host: bt_wakeup=?1? and bt controller : bt_clk_req_out_1=? a?
general specification STA2500D 36/57 doc id 16067 rev 1 bt_host_wakeup to ?1? in order to warm th e host and traffic starts when the host puts bt_uart_cts to low. this is illustrated in figure 12 . 2. autonomous wake-up with communication (i.e. initiated by the STA2500D) the STA2500D first asks the host to restart the system clock by setting bt_clk_req_out_1 to ?1?. when the clock is available, the STA2500D requests traffic by asserting host_wakeup high. then either it puts bt_uart_rts low to start traffic exchange directly or it waits for the host to fi rst assert bt_wakeup hi gh. the selection in between the two behaviours is done by a sw parameter in the parameter file. 3. an autonomous wake-up without communication (i.e. initiated by the STA2500D) the STA2500D asks the host to restart the system clock by setting bt_clk_req_out_1 to ?1?. the uart signals are not changing. figure 11. entering deep sleep mode, pending data on uart interface, through uart with handshake 1. host puts bt_wakeup low. bt controller notices it. but as there is pending traffic to be send to host, it keeps host_wakeup high as long as needed for up-transmission and then de-asserts host_wakeup, telling the host there is nothing more to transmit. 2. bt controller puts uart_rts high to set ?flow off?. this is done in fixed number of instructions. 3. then bt controller puts clk_req_out_1 to ?0?, telling the host it can cut the clock. this is done in fixed number of instructions. 4. there is no clock, bt is in deep sleep mode. ref_clk_in clk_req_out_1 bt_wakeup uart_rts 12 uart_rts host_wakeup 3 4 ref_clk_in clk_req_out_1 bt_wakeup uart_rts 12 uart_rts host_wakeup 3 4
STA2500D general specification doc id 16067 rev 1 37/57 figure 12. wakeup by host through uart with handshake 5. host pulls bt_wakeup high to wake-u p bt controller. hw starts driving clk_req_out_1 high (after 2*lp_clk). 6. host starts 13 mhz clock and dist ribute it when stable. delay between clq_req_out_1 and usage of stable clock is programmable in between 3 and 39 ms. 7. when bt controller starts with clock, it sets ?flow on? by putting uart_rts low. there is a fixed sw latency. host can send commands. 8. bt controller sets host_wakeup high telling to the host it has events to send to the host. 9. when the host is ready for data transmission, it asserts uart_cts low. 6.11 patch ram the STA2500D includes a hw block that allows patching of the rom code. additionally, a sw patch mechanism allows replacing complete sw functions without changing the rom image. a part of the ram memory is used for hw and sw patches. 6.12 download of sw parameter file to change the device configuration a set of customizable parameters have been defined and put together in one file, the parameter file. this parameter file is downloaded at start- up into the STA2500D. examples of parameters are: radio configuration, pcm settings etc. the same hci command is used to download the file containing the patches (both those for the sw and hw mechanism). a more detailed description of the sw parameter file is available upon request. ref_clk_in clk_req_out_1 bt_wakeup uart_rts 5 7 uart_cts uart_rts host_wakeup 8 6 9 uart_rts
general specification STA2500D 38/57 doc id 16067 rev 1 6.13 bluetooth - wlan coexis tence in collocated scenario the coexistence interface uses up to 4 wlan control signal pins, which can be mapped via software parameter download on different pins of the STA2500D (see section 7.5 ). the functionality of the 4 wlan control signal pins depends on the selected algorithm, as explained below and summarized in ta bl e 2 5 . bluetooth and wlan 802.11 b/g [] [] technologies occupy the same 2.4 ghz ism band. the STA2500D implements a set of mechanisms to avoid interference in a collocated scenario. the STA2500D supports 5 different algorithms in order to provide efficient and flexible simultaneous functionality between the two technologies in collocated scenarios: algorithm 1: pta (packet traffic arbitration) based coexistence algorithm defined in accordance with the ieee 802.15.2 recommended practice []. algorithm 2: the wlan is the master and it indicates to the STA2500D when not to operate in case of simultaneous use of the air interface. algorithm 3: the STA2500D is the master and it indicates to the wlan chip when not to operate in case of simultaneous use of the air interface. algorithm 4: two-wire mechanism algorithm 5: alternating wireless medium access (awma), defined in accordance with the wlan 802.11 b/g [] [] technologies. the algorithm is selected via an hci command. the default algorithm is algorithm 1. 6.13.1 algorithm 1: pta (pac ket traffic arbitration) the algorithm is based on a bus connection between the STA2500D and the wlan chip: figure 13. pta diagram by using this coexistence interface it is possib le to dynamically alloca te bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. the algorithm involves a priority mechanism, which allows preserving the quality of certain types of link. a mechanism to indicate that a periodic communication is ongoing. a typical application would be to guarantee optimal quality to the bluetooth voice communication while an intensive wlan communication is ongoing. several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. st specific hci commands are implemented to select the algorithm and to tune the priority handling. stlc2500 d wlan rf_request status freq rf _ confirm
STA2500D general specification doc id 16067 rev 1 39/57 the combination of time division multiplexing and the priority mechanism avoids the interference due to packet collis ion. it also allows the maxi mization of the 2.4 ghz ism bandwidth usage for both devices while preserving the quality of some critical types of link. 6.13.2 algorithm 2: wlan master in case the STA2500D has to cooperate, in a collocated scenario, with a wlan chip not supporting a pta based algorithm, it is possible to put in place a simpler mechanism. the interface is reduced to 1 line: figure 14. wlan master when the wlan has to operate, it alerts high the bt_rf_not_allowed signal and the STA2500D will not operate while this signal stays high. this mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the bluetooth links. 6.13.3 algorithm 3: bluetooth master this algorithm represents the symmetrical case of algorithm 2. also in this case the interface is reduced to 1 line: figure 15. bluetooth master when the STA2500D has to operate it alerts high the wlan_rf_not_allowed signal and the wlan will not operate while this signal stays high. this mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it provides high quality for all bluetooth links but cannot provide guaranteed quality over the wlan links. 6.13.4 algorithm 4: two-wire mechanism based on algorithm 2 and 3, the host decides, on a case-by-case basis, whether wlan or bluetooth is master.the master role can be checked and changed at run-time by the host via an hci command. stlc2500 d wlan bt_rf_not_allowed stlc2500 d wlan wlan_rf_not_allowed
general specification STA2500D 40/57 doc id 16067 rev 1 6.13.5 algorithm 5: alternatin g wireless medium access (awma) awma utilizes a portion of the wlan beacon interval for bluetoot h operations. from a timing perspective, the medium assignment alternates between usage following wlan procedures and usage following bluetooth procedures. the timing synchronization between the wlan and the STA2500D is done by the hw signal medium_free. table 25. wlan hw signal assignment wlan control signal (see also table 29 ) scenario 1: pta scenario 2: wlan master scenario 3: bt master scenario 4:2-wire scenario 5: awma wlan 1 rf_confirm bt_rf_not_ allowed not used bt_rf_not_ allowed medium_f ree wlan 2 rf_request not used wlan_rf_not_ allowed wlan_rf_not_ allowed not used wlan 3 status not used not used not used not used wlan 4 freq (optional) not used not used not used not used
STA2500D digital interfaces doc id 16067 rev 1 41/57 7 digital interfaces 7.1 the uart interface the STA2500D contains a 4-pin (bt_uart_rxd, bt_uart_txd, bt_uart_rts, and bt_uart_cts) uart compatible with 16450, 16550 and 16750 standards. it is running up to 4000 kbps (+1.5% / -1%). the configuration is 8 data bits, 1 start bit, 1 stop bit, and no parity bit. the transmit and receive paths contain a dma function for low cpu load and high throughput. auto rts/cts is implemented in hw, controllable by sw. the uart accepts all hci commands as described in the bluetooth specification, it supports h4 proprietary commands and the deep sleep mode entry and wake-up through h4 uart (see section : deep sleep mode entry and wake up through h4 uart ). the complete list of supported proprietary hci commands is available upon request. at startup, the uart baud rate is fixed at 115200 bps independently of the bt_ref_clk_in frequency. a specific hci command is provided to change the uart baud rate when necessary within the range 9600 bps to 4000 kbps. all standard baud rates and many other ones are supported. 7.2 the spi interface the physical spi interface is made up of 5 sign als: clock, chip select, data in, data out and interrupt. when the spi mode is selected, these signals are available through the bt_uart/bt_spi and bt_host_wakeup pins. figure 16. spi interface spi_csn (on pin bt_uart_rts/bt_spi_csn): ch ip select allows the use of multiple slaves (1 chip select per slave). this signal is active low. this signal is mandatory, even with only 1 slave, because the host must drive this signal to indicate spi frames. spi_clk (on pin bt_uart_cts/bt_spi_clk): clock signal, active for a multiple of data length cycles during an spi transfer (spi_csn active). the clock is allowed to be active when spi_csn is not active, in order to serve other slaves. spi_do (on pin bt_uart_txd/bt_spi_do): data transfer from slave to master. data is generated on the negative edge of spi_clk by the slave and sampled on the host bt controller spi_clk spi_csn spi_do spi_di spi_int spi_clk spi_csn spi_miso spi_mosi spi_int
digital interfaces STA2500D 42/57 doc id 16067 rev 1 positive edge of spi_clk. when spi_csn is inactive, this bt controller output is in tristate mode. spi_di (on pin bt_uart_rxd/bt_spi_di): data transfer from master to slave. data is generated on the negative edge of spi_clk by the master and sampled on the positive edge of spi_clk. spi_int (on pin bt_host_wakeup/bt_spi_int): interrupt from the slave, used to request an spi transfer by the slave to the master. the signal is active high (host input must be level sensitive). the spi interface is master at the host side, and slave at bluetooth controller side. it is designed to work with the h4 and enhanced h4 protocol. also synchronous data packet transfer (esco) over hci is supported. the spi data length and endianness are configurable. the spi interface can only operate in half duplex mode. also the use of flow control is configurable. the flow control consists of an indication from the bluetooth controller whether its receive buffers are ready to receive data. this indication is available in three ways: on the spi_do during t scs (time between spi_csn becoming active and spi_clk becoming high), see fc in figure 17 and tscs in figure 18 in a register that can be read by the host optionally on one of the programmable gpios: gpio_16. this is enabled by a sw parameter download, see section 7.5 the default spi configuration is: half duplex mode 16 bit data length most significant byte first most significant bit first flow control on spi_do and in a register more detailed information on the spi interface is available upon request. figure 17. spi data transfer timing for data length of 8 bits and lsb first, full duplex z fcb0b1b2b3b4b5b6b7 z b0 b1 b2 b3 b4 b5 b6 b7 spi_csn spi_clk spi_do spi_di spi_int
STA2500D digital interfaces doc id 16067 rev 1 43/57 figure 18. spi setup and hold timing 7.3 the pcm interface the chip contains a 4-pin direct voice interface to connect to standard codec. the interface supports multiport pcm operations for voice transfer. it can be programmed to act as a master or a slave via a sw parameter download or via specific hci commands. the four signals of the multi-port pcm interface are: pcm_clk : pcm clock pcm_sync : pcm 8 khz sync (every 125 s) pcm_a : pcm data (tx or rx) pcm_b : pcm data (rx or tx) as a master the interface by default generates a pcm clock rate of 2048 khz, but it can be configured to rates from 8 khz up to 2048 khz. as a slave, it can automatically handle external pcm clock rates from 128 khz up to 4000 khz. the default pcm_sync rate is 8 khz. the following external pcm data format are supported: linear (13 - 16 bit), ? law (8 bit) or a- law (8 bit). table 26. spi timing parameters symbol description min. typ. max. unit p cl spi_clk full period 70 0 0 ns t clh high period of spi_clk 16.6 ns t cll low period of spi_clk 26.4 ns t csh high period of spi_csn 1 * p cl ns t csl low period of spi_csn 9 * p cl ns t scs setup time, spi_csn low to spi_clk high 1 * p cl ns t scl setup time, spi_clk low to spi_csn high 1 / 2 * p cl ns t sdc setup time, spi_mosi valid to spi_clk high 9.7 5 ns t hcd hold time, spi_mosi valid after spi_clk high 0ns t scld setup time, spi_clk low to spi_miso valid 26.5 ns spi_csn spi_clk spi_di spi_do t csl t csh t scl t cll t clh t scs p cl t scld t sdc t hcd
digital interfaces STA2500D 44/57 doc id 16067 rev 1 in slave mode, all possible pcm_sync lengths ar e supported (including ?short frame? (= 1 pcm_clk period) and ?long frame? (> 1 pcm_clk period)). in master mode, the length is configurable (1 (?short frame?), 8 or 16 (?long frame?) pcm_clk periods). the start of the pcm data is configurable. one possible configuration is e.g. for a short frame, the falling edge of the pcm_sync indi cating the start of the pcm word. another possible configuration is e.g. for a long frame, the rising edge of the pcm_sync indicating the start of the pcm word. tx data are by default generated on the positive edge of pcm_clk and expected to be latched by the external device on the negative edge while rx data are latched on the negative edge of pcm_clk. but the inverted clock mode is also supported, whereby the generation of tx data is on the negative edge and the latching of tx and rx data is on the positive edge. one additional pcm_sync signal can be provided via the gpios. see section 7.5 for more details. figure 19. pcm (a-law, -law) standard mode figure 20. linear mode figure 21. multislot operation the pcm implementation supports from 1 up to 3 slots per frame with the following parameters: d02tl558 pcm_clk pcm_sync pcm_a b b pcm_b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b 125s b d02tl559 pcm_clk pcm_sync pcm_a pcm_b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 125 s
STA2500D digital interfaces doc id 16067 rev 1 45/57 figure 22. pcm interface timing table 27. pcm interface parameters symbol description min. typ. max. unit pcm interface f pcm_clk frequency of pcm_clk (slave) 128 (1) 2048 4000 (2) khz f pcm_sync frequency of pcm_sync - 8 - khz p sync_delay delay of the starting of the first slot 0 - 255 cycles s s slot start (programmable for every slot) 0 - 255 cycles d data size 8 - 16 bits n number of slots per frame 1 - 3 - 1. note that it is not possible to use 16 bits in slav e case if pcm_clk is 128khz. this is the only exception. 2. in master case, the maximum of pcm_clk is 2048 khz. table 28. pcm interface timing (at pcm_clk = 2048 khz) symbol description min. typ. max. unit t wch high period of pcm_clk 200 - - ns t wcl low period of pcm_clk 200 - - ns t wsh high period of pcm_sync 200 - - ns t ssc setup time, pcm_sync high to pcm_clk low 100 - - ns t sdc setup time, pcm_a/b input va lid to pcm_clk low 100 - - ns t hcd hold time, pcm_clk low to pcm_a/b input valid 100 - - ns t dcd delay time, pcm_clk high to pcm_a/b output valid - - 150 ns d02tl557 pcm_clk t wcl pcm_sync pcm_a/b in pcm_b/a out msb msb-1 msb-2 msb-3 msb-4 msb msb-1 msb-2 msb-3 msb-4 t ssc t wch t wsh t hcd t sdc t dcd
digital interfaces STA2500D 46/57 doc id 16067 rev 1 7.4 the jtag interface the jtag interface is complia nt with the jtag ieee standard 1149.1. it allows both the boundary scan of the digital pins and the debug of the arm7tdmi application when connected with the standard arm7 developments tools. it is also used for the industrial test of the device. the jtag interface is available through the following 5 pins: bt_gpio_8, bt_gpio_9, bt_gpio_10, bt _gpio_11 and bt_gpio_16. 7.5 alternate i/o functions the STA2500D has 10 additional general purp ose pins on top of the 4 pcm pins, the 4 uart pins and bt_clk_req_out_1 that can also be reconfigured. they are fully programmable via specific hci commands. they can be configured as input, output, interrupt with asynchronous or synchronous edge or level detection and/or wake-up. the alternative functions are: wake-up by the host in deep sleep mode through uart or spi with handshake (see section : deep sleep mode entry and wake-up through h4 uart or h4 spi with handshake ) wlan coexistence control i2c interface pcm synchronization gpios uart / spi interface external driver/lna control for class 1 operation. 19 pins can be redefined by sw to perfor m other functions. pin bt_host_wakeup e.g. can be redefined to perform up to 7 functions, depending on sw settings. 4 exemplary combinations of pin programmings are given in ta bl e 2 9 . the available functions are ex. 1: uart + i2c + class 1 control ex. 2: uart + wlan + class 1 control ex. 3: spi + wlan + class 1 control ex. 4: spi + wlan + i 2 c + class 1 control (the complete list of alternate functions is available upon request). table 29. examples of bt_gpio pin programming STA2500D pin name ex. 1 ex. 2 ex. 3 ex. 4 bt_uart_rxd/bt_spi_di uart_ rxd uart_rxd spi_di spi_di bt_uart_txd/bt_spi_do uart_ txd uart_txd spi_do spi_do bt_uart_cts/bt_spi_clk uart_cts uart_cts spi_clk spi_clk bt_uart_rts/bt_spi_csn uart_rts uart_rts spi_cs spi_cs bt_pcm_clk pcm_clk pcm_clk pcm_clk pcm_clk bt_pcm_sync pcm_sync pcm_sync pcm_sync pcm_sync bt_pcm_a pcm_a pcm_a pcm_a pcm_a
STA2500D digital interfaces doc id 16067 rev 1 47/57 7.6 the i 2 c interface the i 2 c interface is used to access i2c peripherals. the interface is a fast master i 2 c; it has full control of th e interface at all times. i 2 c slave functionality is not supported. bt_pcm_b pcm_b pcm_b pcm_b pcm_b bt_gpio_0 i2c_clk wlan1 wlan1 wlan1 bt_clk_req_in_1 i2c_dat wlan2 wlan2 i2c_dat bt_clk_req_in_2 gpio_2 wlan3 wlan3 wlan3 bt_host_wakeup/bt_spi _int host_wakeup wlan4 spi_int spi_int bt_gpio_11 ant_switch ant_ switch ant_sw itch wlan2 bt_gpio_9 pa_level2 pa_level2 pa_level2 pa_level2 bt_gpio_10 pa_level1 pa_level1 pa_level1 pa_level1 bt_gpio_8 rx_enable rx_en able rx_enable rx_enable bt_gpio_16 pa_enable pa_enable pa_enable pa_enable bt_clk_req_out_1 clk_req_out_1 clk_r eq_out_1 clk_req_out_1 clk_req_out_1 bt_clk_req_out_2 na na wlan4 ic2_clk table 29. examples of bt_gpio pin programming (continued) STA2500D pin name ex. 1 ex. 2 ex. 3 ex. 4
hci transport layer STA2500D 48/57 doc id 16067 rev 1 8 hci transport layer the STA2500D supports the hci transport layer as defined by the sig: h4 []. it is supported in combination with uart and spi mode. the STA2500D also supports an enhanced version of the h4 protocol in combination with spi mode. 8.1 h4 uart transport layer the objective of hci uart transport layer is to make it possible to use bluetooth hci over a serial interface between two uarts on the same pcb. the hci uart transport layer assumes that the uart communication is free from line errors. uart settings the hci uart transport layer uses the following settings for rs232: baud rate :configurable (default baud rate 115200 bps) number of data bits :8 parity bit :no parity stop bit :1 stop bit flow control :rts/cts flow-off response time :500 s the flow-off response time de fines the maximum time that the STA2500D can still receive data after setting rts high. rts/cts flow control is used to prevent temporary uart buffer overrun between the bluetooth controller and the host. the rs232 signals should be connected in a null-modem fashion, i.e. the bluetooth controller txd output should be connected to the host rxd input and the bluetooth controller rts output should be connected to the host cts input and vice versa. if the bluetooth controller rts output (connected to the host cts input) is low, then the host is allowed to send. if the bluetooth controller rts output (connected to the host cts input) is high, then the host is not allowed to send. if the bluetooth controller cts input (connected to the host rts output) is low, then the bluetooth controller is allowed to send. if the bluetooth controller cts input (connected to the host rts output) is high, then the bluetooth controller is not allowed to send. figure 23. uart transport layer bluetooth host bluetooth host controller bluetooth hci hci uart transport layer
STA2500D hci transport layer doc id 16067 rev 1 49/57 8.2 enhanced h4 spi transport layer this is the default spi mode. the enhanced h4 protocol is based on the h4 pr otocol as defined by the sig []. in addition a messaging protocol is defined for contro lling the deep sleep mode entry and wake-up, see section : deep sleep mode entry and wake-up through enhanced h4 spi . three messages are defined: sleep, wakeup and woken. more details on the messages are available upon request. at spi level, the default configuration is used: the spi interface works in half duplex mode the data are exchanged in multiple of 16 bits the most significant byte first the most significant bit first there is a read and write command from the host to access the bluetooth device the bluetooth device requests a transfer by the activation of the interrupt line flow control on spi_do and in a register 8.3 h4 spi transport layer as stated in the previous section, the spi interface is configurable. one possible configuration is the follo wing, implementing a simple h4 spi transport layer. the spi interface works in half duplex mode the data are exchanged in multiples of 8 bits the least significant bit first there is a read and write command from the host to access the bluetooth device the bluetooth device requests a transfer by the activation of the interrupt line flow control on bt_spi_do and in a register 8.4 esco over hci the STA2500D supports synchronous data packet transfer (esco) over hci.
package information STA2500D 50/57 doc id 16067 rev 1 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 24. lfbga48 (6x6x1.4mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.250 0.0492 a1 0.210 0.0083 a2 0.890 0.0350 a3 0.300 0.0118 a4 0.600 0.0236 b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 5.850 6.000 6.150 0.2303 0.2362 0.2421 d1 4.800 0.1890 e 5.850 6.000 6.150 0.2303 0.2362 0.2421 e1 4.800 0.1890 e 0.800 0.0315 f 0.600 0.0236 ddd 0.100 0.0039 eee 0.150 0.0059 fff 0.080 0.0031 lfbga48 l ow profile f ine pitch b all g rid a rray 8092328 b body: 6 x 6 x 1.4mm
STA2500D package information doc id 16067 rev 1 51/57 figure 25. package markings note: the eco level is reflecte d in the ?order code? (see ta bl e 1 ) table 30. package markings legend item description format value a type + version xxxxxx 2500d7 b assembly plant p - c be sequence (ll) ll - d assembly year (y) y - e assembly week (ww) ww - f second_lvl_intct - - g standard st logo - - hdot (pin a1) - - a b d e g f h c
references STA2500D 52/57 doc id 16067 rev 1 10 references table 31. references id short name name date owner [1] - specification of the bluetooth system v2.1 + edr (?lisbon?) not yet released bluetooth sig [2] - specification of the bluetooth system v2.0 + edr november 2004 bluetooth sig [3] - specification of the bluetooth system v1.2 november 2003 bluetooth sig [4] - specification of the bluetooth system - host controller interface [transport layer] volume 04 revision 1.2 or later, 2006, part a: uart v1.1 january 2006 bluetooth sig [5] - radio frequency test suite structure (tss) and test purposes (tp) system specification 1.2/2.0/2.0 + edr, document number rf.ts/2.0.e.3 march 2005 bluetooth sig [6] - ieee 802.15.2, ieee re commended practice for telecommunications and information exchange between systems ? local and metropolitan area networks specific requirements - part 15.2: coexistence of wireless personal area networks with other wireless devices operating in unlicensed frequency band august 2003 ieee [7] wlan ieee 802.11, ieee standards fo r information technology -- telecommunications and information exchange between systems -- local and metropolitan area network -- specific requirements -- part 11: wireless lan medium access control (mac) and physical layer (phy) specifications 1999 ieee [8] 802.11b ieee 802.11b, supplement to 802.11-1999, wireless lan mac and phy specifications: higher speed physical layer (phy) extension in the 2.4 ghz band 1999 ieee [9] 802.11g ieee 802.11g, ieee standard for information technology? telecommunications and information exchange between systems?local and metropolitan area networks?specific requirements?part 11: wireless lan medium access control (mac) and physical layer (phy) specifications? amendment 4: further higher-speed physical layer extension in the 2.4 ghz band 2003 ieee [10] - stlc2500c_ds_rev2.0.pdf, datasheet of bluetooth 2.0&edr compliant single chip, rev2.0 or later --
STA2500D acronyms and abbreviations doc id 16067 rev 1 53/57 11 acronyms and abbreviations table 32. acronyms and abbreviations acronyms/ abbreviation description 2-dh12- dh32-dh5 bluetooth 2 mbps acl packet types 2-ev3 2-ev5 bluetooth 2 mbps synchronous packet types 3-dh1 3-dh3 3-dh5 bluetooth 3 mbps acl packet types 3-ev3 3-ev5 bluetooth 3 mbps synchronous packet types 8-dpsk 8 phase differential phase shift keying a/d analog to digital ac alternating current acl asynchronous connection oriented ahb advanced high-performance bus a-law audio encoding standard amba advanced micro-controller bus architecture amr absolute maximum rating apb advanced peripheral bus arm7 micro-processor arm7tdmi micro-processor awma alternating wireless medium access bb base band ber bit error rate bom bill of materials br basic rate bt bluetooth bw band width c/i carrier-to-co-channel interference cmos complementary metal oxide semiconductor codec coder decoder cpu central processing unit cqddr channel quality driven data rate change cvsd continuous variable slope delta modulation dc direct current
acronyms and abbreviations STA2500D 54/57 doc id 16067 rev 1 devm differential error vector amplitude dh1 dh3 dh5 bluetooth 1 mbps acl packet types dm1 dm3 dm5 bluetooth 1 mbps acl packet types dma direct memory access dv bluetooth 1 mbps synchronous packet type ebc ericsson technology licensing baseband core edr enhanced data rate eir extended inquiry response epr encryption pause/resume esco extended sco ev3 ev4 ev5 bluetooth 1 mbps synchronous packet types fhs frequency hopping synchronization gfsk gaussian frequency shift keying gpio general purpose i/o pin gsm global system for mobile communications h4 uart based hci transport hci host controller interface hv1 hv3 bluetooth 1 mbps synchronous packet types hw hardware i/o input/output i2c inter-integrated circuit if intermediate frequency ism industrial, scientific and medical jtag joint test action group l2cap logical link control and adaptation protocol lmp link manager protocol lna low noise amplifier lo local oscillator lsto link supervision time out -law audio encoding standard table 32. acronyms and abbreviations (continued) acronyms/ abbreviation description
STA2500D acronyms and abbreviations doc id 16067 rev 1 55/57 /4-dqpsk /4 rotated differential quaternary phase shift keying pa power amplifier pcb printed circuit board pcm pulse code modulation pd pull-down pll phase locked loop ppec pitch-period error concealment pta packet traffic arbitration pu pull-up qos quality of service ram random access memory rc resistance-capacitance rf radio frequency rms root mean squared rom read only memory rs232 ansi/eia/tia-232-f, september 1997, inte rface between data terminal equipment and data circuit-terminating equipment employing serial binary data interchange rssi receive signal strength indication rx receive sco synchronous connection oriented sig bluetooth special interest group spi serial peripheral interface st stmicroelectronics sw software tbd to be defined t esco esco interval t sco sco interval t sniff sniff interval tx transmit uart universal asynchronous receiver/transmitter vco voltage controlled oscillator vga variable gain amplifier wcdma wideband code division multiple access wfbga very very thin profile fine pitch ball grid array wlan wireless local area network wlcsp wafer-level chip scale package table 32. acronyms and abbreviations (continued) acronyms/ abbreviation description
revision history STA2500D 56/57 doc id 16067 rev 1 12 revision history table 33. document revision history date revision changes 24-jul-2009 1 initial release.
STA2500D doc id 16067 rev 1 57/57 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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